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Support full UVM parsing and XML dump #1538

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veripoolbot opened this issue Oct 6, 2019 · 4 comments
Open

Support full UVM parsing and XML dump #1538

veripoolbot opened this issue Oct 6, 2019 · 4 comments

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@veripoolbot
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@veripoolbot veripoolbot commented Oct 6, 2019


Author Name: Wilson Snyder (@wsnyder)
Original Redmine Issue: 1538 from https://www.veripool.org


Feature tracking bug.

Currently Verilator parses a subset of SystemVerilog and reports many unsupported errors at parse time.

Towards getting full language support, it is desirable that the parser handle all of UVM and support dumping this to XML. This allows downstream tools to use the full language. Any unsupported Verilation language constructs would then be reported at an error at that point.

Verilog-Perl's parser is a nearly complete starting point, with some fixes needed to handle "foo = new foo".

@Millennium-Software-Design

Hi, I'm very interested in this. I'm not sure I fully understand the goal here though. UVM is all non-synthesizable code, and I thought verilator only handled synthesizable code. Is there really a goal to be able to compile and run UVM testenches with verilator?

@wsnyder
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@wsnyder wsnyder commented Feb 23, 2020

The Verilator roadmap is towards eventual complete SystemVerilog support. It's a long road.

@Millennium-Software-Design

Complete support? So arbitrary "#" delays, X and Z, everything?

@wsnyder
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@wsnyder wsnyder commented Feb 26, 2020

In several years, yes. Only those features needed to get to UVM are in the first major round.

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