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Support full UVM parsing and XML dump #1538
Feature tracking bug.
Currently Verilator parses a subset of SystemVerilog and reports many unsupported errors at parse time.
Towards getting full language support, it is desirable that the parser handle all of UVM and support dumping this to XML. This allows downstream tools to use the full language. Any unsupported Verilation language constructs would then be reported at an error at that point.
Verilog-Perl's parser is a nearly complete starting point, with some fixes needed to handle "foo = new foo".