Support full UVM testing

[veripoolbot]

This issue tracks the remaining subissues that must be fixed before UVM can be converted to C++. This first comment is updated periodically to summarize the most recent state.

Note UVM is not yet supported, We request you do not file "UVM doesn't work" issues, or "How soon will UVM work" issues. Please try UVM and post here only if you are willing to help develop the subissues mentioned.

For developers, to run UVM, see:

• t_uvm_all test, which exits early so it passes. The early exit in Verilator.cpp needs to be removed.
• t_uvm_todo test, which has commented out code in t_uvm_pkg_todo.vh so it passes. Tthe commented-out code need to be reinserted as issues are resolved,

The list of subissues remaining to be resolved:

• Fix uvm_sequencer wrong reference type #4497
• Fix VlProcess argument breaks DPI export #4566
• Fix virtual interface "combinational region did not converge" error #5116
• Support unassigned virtual interfaces #5265
• Fix coroutine calls inside lambdas #6106

(We know there are additional issues with the UVM test suite that have bugs that are not filed yet, no need to file them until above are done first, thanks.)

[Millennium-Software-Design]

Hi, I'm very interested in this. I'm not sure I fully understand the goal here though. UVM is all non-synthesizable code, and I thought verilator only handled synthesizable code. Is there really a goal to be able to compile and run UVM testenches with verilator?

[wsnyder]

The Verilator roadmap is towards eventual complete SystemVerilog support. It's a long road.

[Millennium-Software-Design]

Complete support? So arbitrary "#" delays, X and Z, everything?

[wsnyder]

In several years, yes. Only those features needed to get to UVM are in the first major round.

[mkacen]

Any update on the UVM support?
I am trying to run System Verilog TB with UVM and I get many parsing errors:
Error: /tools/snps/vcs/Q-2020.03-SP2/etc/uvm-1.2/base/uvm_version.svh:31:31: syntax error, unexpected $end, expecting TYPE-IDENTIFIER
31 | parameter string uvm_revision =
| ^
/tools/snps/vcs/Q-2020.03-SP2/etc/uvm-1.2/base/uvm_coreservice.svh:221:1: ... note: In file included from uvm_coreservice.svh
/tools/snps/vcs/Q-2020.03-SP2/etc/uvm-1.2/base/uvm_base.svh:28:37: ... note: In file included from uvm_base.svh
/tools/snps/vcs/Q-2020.03-SP2/etc/uvm-1.2/dpi/uvm_regex.svh:25:67: ... note: In file included from uvm_regex.svh
/tools/snps/vcs/Q-2020.03-SP2/etc/uvm-1.2/dpi/uvm_svcmd_dpi.svh:45:59: ... note: In file included from uvm_svcmd_dpi.svh
/tools/snps/vcs/Q-2020.03-SP2/etc/uvm-1.2/dpi/uvm_hdl.svh:130:159: ... note: In file included from uvm_hdl.svh
/tools/snps/vcs/Q-2020.03-SP2/etc/uvm-1.2/uvm_pkg.sv:28:17: ... note: In file included from uvm_pkg.sv

[wsnyder]

UVM support is still in progress and a lot left to do, let us know if you'd like to help.

[saw235]

UVM support is still in progress and a lot left to do, let us know if you'd like to help.

Hi, I am interested in helping. Where can I start learning about the things needed. I've tried running with --language 1800-2017 but am getting

%Error: ../src/my_design_0.1.0/testbench/tb_top.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: new

[wsnyder]

Hi, @saw235 would love to have additional help on this. Given the error message I suspect you are using a very old version. Presently the parser can read in UVM code, but cannot elaborate it, so that would be the next phase requiring some work. If you run the verilator_ext_tests repository t/t_uvm_parse.pl test, and comment out the --debug-exit-uvm you can see the errors that next need to be made supported.

[eminakgun]

What is current status here?

[wsnyder]

Fundamentally the message above still applies, it can read but not elaborate, and we would welcome assistance.

There has been progress on recursive functions, and static members, so at least some of the items needed are making progress.

[tuppi-ovh]

Hello, is it possible to have an update about Verilator/UVM integration? It is told that it should be parse-compatible but I have too much parsing errors of UVM SystemVerilog sources (on master branch). Maybe I should use an alternative development branch to get as much UVM functionalities as possible? When a complete Verilator/UVM integration is planned? Thank you in advance for your answer.

[wsnyder]

Version 5 which is in development for release later this year will do correct scheduling and fork/join. Past that, UVM can get parsed, but not evaluated, so a lot left to do, let us know if you'd like to help.

[benjaminmordaunt]

@wsnyder

I'm very interested in understanding what still needs to be accomplished here. I'm currently running the Git master HEAD:

Verilator 4.227 devel rev v4.226-17-g45d622e4

I have cloned the Verilator-patched downstream version of UVM, and have reproduced EDAPlayground's UVM 1.2 Hello World source base for testing. Issuing the following command:

verilator --cc uvm/src/uvm.sv design.sv testbench.sv -Iuvm/src --exe

currently gives:

%Error-PKGNODECL: uvm/src/base/uvm_text_tr_database.svh:135:57: Package/class 'type_id' not found, and needs to be predeclared (IEEE 1800-2017 26.3)
  135 |       uvm_text_tr_stream m_stream = uvm_text_tr_stream::type_id::create(name);
      |                                                         ^~~~~~~
                  uvm/src/base/uvm_tr_database.svh:228:10: ... note: In file included from uvm_tr_database.svh
                  uvm/src/base/uvm_links.svh:322:10: ... note: In file included from uvm_links.svh
                  uvm/src/base/uvm_packer.svh:1191:1: ... note: In file included from uvm_packer.svh
                  uvm/src/base/uvm_comparer.svh:691:1: ... note: In file included from uvm_comparer.svh
                  uvm/src/base/uvm_printer.svh:1901:1: ... note: In file included from uvm_printer.svh
                  uvm/src/base/uvm_copier.svh:208:1: ... note: In file included from uvm_copier.svh
                  uvm/src/base/uvm_field_op.svh:176:1: ... note: In file included from uvm_field_op.svh
                  uvm/src/base/uvm_policy.svh:186:1: ... note: In file included from uvm_policy.svh
                  uvm/src/base/uvm_config_db.svh:406:1: ... note: In file included from uvm_config_db.svh
                  uvm/src/base/uvm_resource_db_options.svh:108:1: ... note: In file included from uvm_resource_db_options.svh
                  uvm/src/base/uvm_resource_db.svh:380:1: ... note: In file included from uvm_resource_db.svh
                  uvm/src/base/uvm_resource_specializations.svh:197:1: ... note: In file included from uvm_resource_specializations.svh
                  uvm/src/base/uvm_resource.svh:1423:1: ... note: In file included from uvm_resource.svh
                  uvm/src/base/uvm_resource_base.svh:547:1: ... note: In file included from uvm_resource_base.svh
                  uvm/src/base/uvm_spell_chkr.svh:204:1: ... note: In file included from uvm_spell_chkr.svh
                  uvm/src/base/uvm_queue.svh:211:1: ... note: In file included from uvm_queue.svh
                  uvm/src/base/uvm_pool.svh:338:77: ... note: In file included from uvm_pool.svh
                  uvm/src/base/uvm_registry.svh:676:1: ... note: In file included from uvm_registry.svh
                  uvm/src/base/uvm_factory.svh:2107:1: ... note: In file included from uvm_factory.svh
                  uvm/src/base/uvm_object.svh:1375:1: ... note: In file included from uvm_object.svh
                  uvm/src/base/uvm_globals.svh:508:10: ... note: In file included from uvm_globals.svh
                  uvm/src/base/uvm_coreservice.svh:443:1: ... note: In file included from uvm_coreservice.svh
                  uvm/src/base/uvm_misc.svh:509:1: ... note: In file included from uvm_misc.svh
                  uvm/src/base/uvm_object_globals.svh:717:40: ... note: In file included from uvm_object_globals.svh
                  uvm/src/base/uvm_version.svh:38:1: ... note: In file included from uvm_version.svh
                  uvm/src/base/uvm_base.svh:30:38: ... note: In file included from uvm_base.svh
                  uvm/src/dpi/uvm_regex.svh:25:67: ... note: In file included from uvm_regex.svh
                  uvm/src/dpi/uvm_svcmd_dpi.svh:45:59: ... note: In file included from uvm_svcmd_dpi.svh
                  uvm/src/dpi/uvm_hdl.svh:128:93: ... note: In file included from uvm_hdl.svh
                  uvm/src/uvm_pkg.sv:28:16: ... note: In file included from uvm_pkg.sv
                  uvm/src/uvm.sv:26:1: ... note: In file included from uvm.sv
                  ... For error description see https://verilator.org/warn/PKGNODECL?v=4.227

I first want to make sure this is an expected error and I'm not just running this incorrectly.
Then, would you mind giving a brief A-to-Z of work that still needs to be done here? Thanks! :)