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Improve internal elaboration algorithm #1540

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veripoolbot opened this issue Oct 6, 2019 · 0 comments
Open

Improve internal elaboration algorithm #1540

veripoolbot opened this issue Oct 6, 2019 · 0 comments

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@veripoolbot veripoolbot commented Oct 6, 2019


Author Name: Wilson Snyder (@wsnyder)
Original Redmine Issue: 1540 from https://www.veripool.org


Feature tracking bug.

Verilator implements elaboration using an algorithm that goes back to its birth and predates their being a IEEE standard. Basically it reads every needed module up front, then links, then determines parameter resolution, and finally deletes what was not needed.

The elaboration process should be as described in IEEE, with parsing of modules etc done as parameters are resolved. This is what is ideally needed for #�, #�, #�, #�.

Internally this should simplify V3LinkDot, though will result in tighter coupling of many of the early stages which needs to be planned out.

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