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Verilated Model did not DC converge #1549

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veripoolbot opened this issue Oct 14, 2019 · 4 comments
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Verilated Model did not DC converge #1549

veripoolbot opened this issue Oct 14, 2019 · 4 comments
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@veripoolbot veripoolbot commented Oct 14, 2019


Author Name: hamza shabbir
Original Redmine Issue: 1549 from https://www.veripool.org

Original Assignee: Auto Update Daemon (@veripool-bot)


I am implementing a SAP-1 architecture in verilator. While using the make command i am facing an error VSAP:cpp:95 Verilated Model did not DC converge. can anyone help me with this. why i am getting this error and how can i solve it. and what is the cause of this error

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@veripoolbot veripoolbot commented Oct 14, 2019


Original Redmine Comment
Author Name: Todd Strader (@toddstrader)
Original Date: 2019-10-14T09:38:01Z


See the section of the --help titled: Verilated model didn't converge. There are instructions in there for isolating and resolving the issue. The "DC" part of the message means that the issue occurred during the initial phase.

I'm just guessing here without code to look at, but please note that Verilator ignores delay (#) statements. If you're porting something from an event simulator that can get you in trouble. Again, see the manual for a discussion on this.

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@veripoolbot veripoolbot commented Oct 15, 2019


Original Redmine Comment
Author Name: hamza shabbir
Original Date: 2019-10-15T04:54:47Z


The below files contain the code, Make file and test file. i still cant figure out how to solve the Dc converge issue.

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@veripoolbot veripoolbot commented Oct 15, 2019


Original Redmine Comment
Author Name: Todd Strader (@toddstrader)
Original Date: 2019-10-15T09:49:26Z


Couple things here:

I'd really suggest properly indenting your designs. I couldn't make sense of SAP.v until I did so.

Your design isn't clocked. There is a clk signal, but it is never used and none of the always blocks have edge sensitivity. Since you only have always @(*) blocks, it's not a great surprise to me that your design which is a big feedback loop doesn't settle. To learn more, I'd suggest googling something like "clocking digital logic in verilog".

What's not great here is the usability of this error message. It's clear enough what is happening, but it doesn't really help you debug it. I don't want to hijack your issue, so I'll open a related one for the usability of the error.

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@veripoolbot veripoolbot commented Oct 15, 2019


Original Redmine Comment
Author Name: hamza shabbir
Original Date: 2019-10-15T09:54:07Z


thank you but the issue has been solved

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