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There is a problem when Handling variables forced type conversion #1554

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veripoolbot opened this issue Oct 15, 2019 · 6 comments
Open

There is a problem when Handling variables forced type conversion #1554

veripoolbot opened this issue Oct 15, 2019 · 6 comments

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@veripoolbot veripoolbot commented Oct 15, 2019


Author Name: w z
Original Redmine Issue: 1554 from https://www.veripool.org

Original Assignee: Todd Strader (@toddstrader)


The result of this shift should be related to the bit width of the operation. For example, the previous operation value is only 1 bit, and only 1 bit after shifting, taking a value lower than 1 bit.
Need to specify the variable bit width according to the conversion bit width.

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@veripoolbot veripoolbot commented Oct 15, 2019


Original Redmine Comment
Author Name: Todd Strader (@toddstrader)
Original Date: 2019-10-15T11:14:17Z


See the WIDTH section of the manual. I'd provide some examples from other simulators but EDA Playground seems to be having some issues right now. Also, see 11.8.1 of the LRM. Specifically:

The sign and size of any self-determined operand are determined by the operand itself and independent of the remainder of the expression.

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@veripoolbot veripoolbot commented Oct 15, 2019


Original Redmine Comment
Author Name: w z
Original Date: 2019-10-15T11:55:26Z


we also use CARBON's CMS tool,the result in line with expectations, it can correctly do type conversion with width variation, Maybe you can learn from its implementation.

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@veripoolbot veripoolbot commented Oct 16, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-10-16T00:49:16Z


Can you submit a self-checking test, ideally in the test_regress format (see the manual), and ideally passing against VCS or NC-Verilog, as they are generally closer to IEEE compliant. Thanks.

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@veripoolbot veripoolbot commented Oct 16, 2019


Original Redmine Comment
Author Name: w z
Original Date: 2019-10-16T01:37:01Z


this is the test code,maybe you can use fore reference.

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@veripoolbot veripoolbot commented Oct 16, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-10-16T02:05:28Z


Please give a ASCII file which is a few lines long which prints e.g. pass or fail. And runs standalone.

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@veripoolbot veripoolbot commented Nov 5, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-11-05T03:10:54Z


Waiting on standalone test case.

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