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Asynchronous reset logic is inconsistent with rtl #1555

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veripoolbot opened this issue Oct 15, 2019 · 2 comments
Closed

Asynchronous reset logic is inconsistent with rtl #1555

veripoolbot opened this issue Oct 15, 2019 · 2 comments
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@veripoolbot veripoolbot commented Oct 15, 2019


Author Name: w z
Original Redmine Issue: 1555 from https://www.veripool.org

Original Assignee: Todd Strader (@toddstrader)


hi,
On RTL, asynchronous reset does not require a falling edge to trigger the initial value.verilaror is inconsistent with rtl.please check.

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@veripoolbot veripoolbot commented Oct 15, 2019


Original Redmine Comment
Author Name: Todd Strader (@toddstrader)
Original Date: 2019-10-15T11:00:39Z


See --x-initial-edge. I think that may resolve your problem.

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@veripoolbot veripoolbot commented Oct 16, 2019


Original Redmine Comment
Author Name: w z
Original Date: 2019-10-16T01:05:14Z


great,thanks very much for your help

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