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Verilog 2001: verilator does not issue a warning on missing 'reg', Webpack ISE 14.7 does. #1570

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veripoolbot opened this issue Oct 20, 2019 · 4 comments
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@veripoolbot veripoolbot commented Oct 20, 2019


Author Name: Jacko Dirks (@jackodirks)
Original Redmine Issue: 1570 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


I used the most recent master commit of verilator to show this problem exists in the current master branch.

Take the following verilog code:

module testmodule (
     input clk,
     input rst,
     output [2:0] val
);

parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4;

reg[3:0] curState = s0;
reg[3:0] nextState = s0;

always @(posedge clk) begin
     if (rst == 1)
         curState <= s0;
     else
         curState <= nextState;
end

always @(curState) begin
     case (curState)
         s0:
             nextState = s1;
         s1:
             nextState = s2;
         s2:
             nextState = s3;
         s3:
             nextState = s4;
         s4:
             nextState = s0;
     endcase
end

always @(curState) begin
     case (curState)
         s0:
             val = 3'H0;
         s1:
             val = 3'H1;
         s2:
             val = 3'H2;
         s3:
             val = 3'H3;
         s4:
             val = 3'H4;
     endcase
end

endmodule
</code>

The output @Val@ should contain the keyword reg. But verilator does not agree:

@verilator -Wall -cc testmodule.v --exe test_top.cpp --trace@

gives no output: everything is fine.
WebPack ISE 14.7 says:


Started : "Check Syntax for testmodule".
Running xst...
Command Line: xst -intstyle ise -ifn /home/jacko/git/ISEproject/testmodule.xst -ofn testmodule.stx

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../temp/testmodule.v" in library work
Module <testmodule> compiled
ERROR:HDLCompilers:247 - "../../temp/testmodule.v" line 37 Reference to vector wire 'val' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "../../temp/testmodule.v" line 37 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "../../temp/testmodule.v" line 39 Reference to vector wire 'val' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "../../temp/testmodule.v" line 39 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "../../temp/testmodule.v" line 41 Reference to vector wire 'val' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "../../temp/testmodule.v" line 41 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "../../temp/testmodule.v" line 43 Reference to vector wire 'val' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "../../temp/testmodule.v" line 43 Illegal left hand side of blocking assignment
ERROR:HDLCompilers:247 - "../../temp/testmodule.v" line 45 Reference to vector wire 'val' is not a legal reg or variable lvalue
ERROR:HDLCompilers:44 - "../../temp/testmodule.v" line 45 Illegal left hand side of blocking assignment
Analysis of file <"testmodule.prj"> failed.
--> 


Total memory usage is 457988 kilobytes

Number of errors   :   10 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)


Process "Check Syntax" failed

Which, to my limited knowledge, is a correct error: the val should be a register.

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@veripoolbot veripoolbot commented Oct 20, 2019


Original Redmine Comment
Author Name: Jacko Dirks (@jackodirks)
Original Date: 2019-10-20T12:06:39Z


I am sorry for the Webpack layout, this is the first time. And I also do not know how to fix it.

The verilator command is acutally:

verilator --default-language 1364-2001 -Wall -cc testmodule.v --exe test_top.cpp --trace

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@veripoolbot veripoolbot commented Oct 20, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-10-20T13:21:40Z


Yes, it should warn, will look into it.

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@veripoolbot veripoolbot commented Nov 6, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-11-06T02:15:52Z


Fixed in git towards eventual 4.022 release.

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@veripoolbot veripoolbot commented Nov 10, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-11-10T19:28:09Z


In 4.022.

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