Fuzzer: Segfault on genvar out of scope #1589
Comments
Original Redmine Comment Generate dosn't make a scope, begin/end does. Basically generate was a Verilog 2001 thing now not needed. Cleaned up warnings & real issue. Fixed in git towards 4.022. |
Original Redmine Comment Regarding the scope: that's interesting. I think you're right but it took me longer to confirm that than I expected. I didn't find anything definitive either way in the standard, and so I tried running:
with ModelSim and it choked because it didn't want to let the genvar be accessible there. Then I tried iverilog and it choked because it couldn't handle printing a genvar at all. And then I tried:
And they both accepted it. Meanwhile, Verilator seems to treat these two cases the same, which seems like the correct thing to do. |
Author Name: Eric Rippey
Original Redmine Issue: 1589 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
Running the attached testcase with:
verilator_bin --lint-only 7.sv
On version:
Verilator 4.020 devel rev v4.020-56-gbcb766b
Produces:
I think there are two different problems here:
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