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Add interface port visibility in traces #1594

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veripoolbot opened this issue Nov 8, 2019 · 3 comments
Closed

Add interface port visibility in traces #1594

veripoolbot opened this issue Nov 8, 2019 · 3 comments
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@veripoolbot veripoolbot commented Nov 8, 2019


Author Name: Todd Strader (@toddstrader)
Original Redmine Issue: 1594 from https://www.veripool.org

Original Assignee: Todd Strader (@toddstrader)


See:
https://github.com/toddstrader/verilator-dev/tree/iface-vcd

Users should not have to know where an interface was instantiated to pull it up in the trace. This adds the interface "module" everywhere there is an interface port. I extended t_interface1_modport_trace to check the VCD and added t_interface1_modport_trace_fst for the FST.

Please let me know what you think. I'm ready to squash and push this one once reviewed.

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@veripoolbot veripoolbot commented Nov 8, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-11-08T12:06:23Z


Good idea.

Only nit is to put braces around the iteration and reorder a bit to clarify how you are save/restoring the variables. e.g.

         // Stash the signal state because we're going to go through another VARSCOPE
         AstVarScope* traVscp = m_traVscp;
         AstNode* traValuep = m_traValuep;
         {
             m_traVscp = NULL;
             m_traValuep = NULL;
             m_ifShowname = m_traShowname;
             m_traShowname = "";
             iterate(nodep->ifacep());
             m_traShowname = m_ifShowname;
             m_ifShowname = "";
         }
         m_traVscp = traVscp;
         m_traValuep = traValuep;

Then feel free to squash push.

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@veripoolbot veripoolbot commented Nov 8, 2019


Original Redmine Comment
Author Name: Todd Strader (@toddstrader)
Original Date: 2019-11-08T14:02:35Z


Done.

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@veripoolbot veripoolbot commented Nov 10, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-11-10T19:28:22Z


In 4.022.

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