Statement label should be allowed to be a duplicate of a parameter

[veripoolbot]

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Author Name: Pieter Kapsenberg
Original Redmine Issue: 1603 from https://www.veripool.org

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This syntax is not allowed by verilator:

module test;
parameter DEMO = 1;
always begin: DEMO
  $finish;
end
endmodule

Results in the following error.
%Error: test.sv:3: Unsupported in C: Block has the same name as variable: DEMO
%Error: test.sv:2: ... Location of original declaration

What exactly is the limitation here? C99 at least does allow this:

#include "stdio.h"

int main() {
  int x = 0;
x:
  printf("x is %d\n", x);
  return 0;

[veripoolbot]

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Original Redmine Comment
Author Name: Pieter Kapsenberg
Original Date: 2019-11-15T02:11:57Z

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Ok well that formatting failed - trying again:

This syntax is not allowed by verilator:

module test;
parameter DEMO = 1;
always begin: DEMO 
  $finish;
end
endmodule

</code>

Results in the following error:

%Error: test.sv:3: Unsupported in C: Block has the same name as variable: DEMO
%Error: test.sv:2: ... Location of original declaration

</code>

What exactly is the limitation here? C99 at least does allow this:

#include "stdio.h"

int main() {
  int x = 0;
x:
  printf("x is %d\n", x);
  return 0;
}

</code>

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-11-15T09:08:38Z

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This is to protect against what in some cases may become:

int foo;
void foo();

which causes a mess of course. Verilator does currently rename some constructs by adding PVT to the names, but this same prefix would be added to both, so there would still be a conflict. Perhaps a different prefix could be used for variables and blocks, but this sort of name collision seems a bad practice, and certainly would be a lint problem regardless, so I'm reluctant to add code and break backward compatibility for it.