for loop initialisation clause skipped

[veripoolbot]

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Author Name: Andrew Holme
Original Redmine Issue: 1605 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

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The body of the first for loop in this code never executes because the condition clause is always false; however it seems the initialise clause is also (incorrectly) optimised away.

module top (
  input  wire       clk,
  input  wire       rst_n,
  output reg  [1:0] out);
  
  reg [1:0] one, nil;
  
  localparam CORES=1;
  
  always @(posedge clk or negedge rst_n) begin
     integer i;
     if (!rst_n) begin
       out <= 2'b0;
       nil <= 2'b0;
       one <= 2'b0;
     end else begin   
       for (i=0; i<CORES-1; i=i+1) begin // should always set i=0
         nil[i] <= 1'b1; // never happens
       end
       // i should always be 0 here; but is 0 only in the first cycle after reset, then 1
       out[i] <= 1'b1;
       for (i=0; i<CORES; i=i+1) begin
         one[i] <= 1'b1;
       end
     end
  end
  
endmodule

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-11-15T23:25:04Z

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Sorry, that's nasty and should have been caught earlier, so fixing immediately.

FWIW "for (i=1; 0; )" was tested, but not this case.

Fixed in git towards eventual 4.024 release.

[veripoolbot]

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Original Redmine Comment
Author Name: Andrew Holme
Original Date: 2019-11-17T11:42:24Z

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Thanks for fixing it so quickly.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-12-08T13:12:51Z

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In 4.024.

For additional support related to this please file new bug.