Strange dotted expression makes Verilator hang, but print correct error message

[veripoolbot]

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Author Name: Bogdan Vukobratovic (@bogdanvuk)
Original Redmine Issue: 1608 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

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The following module makes Verilator hang

module m1
(
);
     typedef logic [3:0] foo_t;

     foo_t foo_s;

     assign bar_s = {foo_s, foo_s}.f1;

endmodule

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-11-20T00:24:16Z

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Thanks for the report.

Fixed in git towards eventual 4.024 release.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-12-08T13:12:44Z

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In 4.024.

For additional support related to this please file new bug.