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Strange dotted expression makes Verilator hang, but print correct error message #1608

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veripoolbot opened this issue Nov 19, 2019 · 2 comments
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@veripoolbot veripoolbot commented Nov 19, 2019


Author Name: Bogdan Vukobratovic (@bogdanvuk)
Original Redmine Issue: 1608 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


The following module makes Verilator hang

module m1
(
);
     typedef logic [3:0] foo_t;

     foo_t foo_s;

     assign bar_s = {foo_s, foo_s}.f1;

endmodule


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@veripoolbot veripoolbot commented Nov 20, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-11-20T00:24:16Z


Thanks for the report.

Fixed in git towards eventual 4.024 release.

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@veripoolbot veripoolbot commented Dec 8, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-12-08T13:12:44Z


In 4.024.

For additional support related to this please file new bug.

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