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Interface declared in parent scope can be used incorrectly #1623
Author Name: Driss Hafdi
If an interface is declared in a module's parent scope, it seems as though the current scope can still use the interface instance as if it was declared locally. While it is a legal systemverilog construct (Section "23.8 Upwards name referencing" in the LRM), it doesn't bode well with synthesis and a warning would be ideal. Here is an small testbench that exposes this issue: drissos@046205a
Original Redmine Comment
Pushed the test_regress/t/t_interface_parent_scope_bad.v test with an unsupported() tag (so doesn't run).
This might be a good one to look at. V3LinkDot does the resolution, and relies on VSymEnt's findIdFallback to recuse upwards.
Perhaps have findIdFallback return (via a ref) a bool if a module boundary was hit (that is it iterated over a SymEnt pointing at a AstNodeModule).
Then add a new warning code in V3Error.h.
The V3LinkDot code is fairly large but hopefully you can understand it, feel free to ask questions.