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`uselib error with Verilator #1634

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veripoolbot opened this issue Dec 11, 2019 · 5 comments
Closed

`uselib error with Verilator #1634

veripoolbot opened this issue Dec 11, 2019 · 5 comments

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@veripoolbot veripoolbot commented Dec 11, 2019


Author Name: Frederic Antonin
Original Redmine Issue: 1634 from https://www.veripool.org


I have some code that use the following construct before a module instantiation.

`uselib lib=FPGA1_lib
 my_module my_module_inst(

I need to add the uselib for inter FPGA simulations because unfortunately I have the same module name with different code/library in each FPGA.

With Verilator I get the following error:

Define or directive not defined: '`uselib'

Is this an unsupported feature?
Is there a work around?

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@veripoolbot veripoolbot commented Dec 11, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-12-11T17:59:36Z


`uselib not only is not supported, it isn't part of the language, and I don't know what it is and don't see much from googling it.

If roughly two big simulators support it, and we can determine what the definition of it is, I would consider a patch to implement it.

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@veripoolbot veripoolbot commented Dec 11, 2019


Original Redmine Comment
Author Name: Frederic Antonin
Original Date: 2019-12-11T18:45:49Z


`uselib is a work around for a Verilog problem. It is supported by both Mentor and Cadence simulators.

Verilog does not have a "formal" concept of library as opposed to VHDL.
The verilog files are sill compiled in libraries by the simulator but there is no way in verilog to say in your code:
This module belongs to this particular library.

No consider what happen when you have 2 modules with the same name (My_module) in 2 different projects (FPGA1 and FPGA2).
If you are simulating one FPGA project at the time then it's not a problem because you only load the libraries related to that particular project.
The simulator will only find one "My_module" while searching through the libraries.

The problem arise when you try to simulate FPGA1 and FPGA2 interacting together.

FPGA1 is compiled in a library called FPGA1_lib and contain a module called "My_module"
FPGA2 is compiled in a library called FPGA2_lib and also contain a module called "My_module"

When the simulator loads the design it searches for a module called "My_module" but now it finds 2 of them (one in FPGA1_lib and one in FPGA2_lib) witch one is the right one for that instance?

`uselib (although not standard) is there to tell the simulator "listen I know there are 2 "My_module" but for this piece of code use the one in that particular library.

I'm not sure if Verilator needs to support that feature but it would be good to at least not flag it as an error.
I'm using Verilator in lint-only mode and that error is preventing it from analyzing the code any further.

Regards

Frederic

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@veripoolbot veripoolbot commented Dec 11, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-12-11T22:11:17Z


Ok, seems reasonable to ignore this then, can you look at patching this?

  1. Add a test to test_regress/t
  2. Update src/verilog.y to look for `uselib followed by spaces followed by whatever's legal (maybe one non-whitespace token? not sure)
  3. See new test pass. Ideally run other tests ("make test").
  4. Add your name to docs/CONTRIBUTORS, and submit the diffs (ideally with a github user name/email)
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@veripoolbot veripoolbot commented Dec 12, 2019


Original Redmine Comment
Author Name: Frederic Antonin
Original Date: 2019-12-12T13:21:38Z


I'm afraid this if beyond my coding skills.
I tried to look into verilog.y to see how other pre processors are treated but I can't find any example.

The valid syntax for `uselib is:

`uselib <library_reference>...

where <library_reference> can be one or more of the following:
dir=<library_directory>
file=<library_file>
libext=<file_extension>
lib=<library_name>

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@veripoolbot veripoolbot commented Dec 13, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-12-13T01:54:39Z


Fixed in git to ignore until end-of-line.

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