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Support signal declarations in loop initialisers #172

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veripoolbot opened this issue Nov 3, 2009 · 6 comments
Closed

Support signal declarations in loop initialisers #172

veripoolbot opened this issue Nov 3, 2009 · 6 comments

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@veripoolbot veripoolbot commented Nov 3, 2009


Author Name: Byron Bradley (@bbradley)
Original Redmine Issue: 172 from https://www.veripool.org
Original Date: 2009-11-03
Original Assignee: Byron Bradley (@bbradley)


Support signal declarations in loop initialisers. Testcase will be attached soon.

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@veripoolbot veripoolbot commented Nov 3, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-11-03T11:27:52Z


This is a great first project as it's mostly the parser. Let me know when/if you'd like to get started.

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@veripoolbot veripoolbot commented Nov 3, 2009


Original Redmine Comment
Author Name: Byron Bradley (@bbradley)
Original Date: 2009-11-03T11:42:26Z


Thanks Wilson, I'm planning on starting this one today, we're aiming to get all four features (102, 170-172) supported in the next few weeks.

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@veripoolbot veripoolbot commented Nov 3, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-11-03T12:05:37Z


Great! I had a bunch of changes staged for 3.800 that I was holding in case there were bugs on 3.700. I could make a branch, but I just pushed them to make patching easier. So be sure to 'git' the latest.

So here's how I'd approach this:

Make a testcase in the t_EXAMPLE format, attach here for reference.

Look at the grammar in the git version of VerilogPerl's src/VParseGrammar.y as this grammar supports what you want. Then copy the appropriate rules to src/verilog.y and modify the productions to match similar variable declaration rules elsewhere in verilog.y. I'd put a AstBegin(unnamed) wrapper over the AstFor, then the variables land under the AstBegin. (You can do that for all For loops even if they don't have variables.) I think this will require minimal changes elsewhere.

Now you can run "test_regress/t/t_{new testcase}.pl --debug" and it'll probably fail but you'll see a test_regress/obj_dir/t_{newtestcase}/*.tree file which you can examine to see if the parsing worked. See also the other test_regress/driver.pl debugging flags.

Good luck, drop me a note as you have questions.

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@veripoolbot veripoolbot commented Nov 9, 2009


Original Redmine Comment
Author Name: Byron Bradley (@bbradley)
Original Date: 2009-11-09T15:33:22Z


Attaching a testcase which has been run in another simulator and a patch to implement the feature in Verilator.

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@veripoolbot veripoolbot commented Nov 10, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-11-10T00:12:51Z


Patch committed for next release 3.730+.

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@veripoolbot veripoolbot commented Feb 7, 2010


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-02-07T12:38:05Z


In 3.800.

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