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Support implicit signals in both branches of a generate(if..else) #201
If an implicit signal appears in both branches of a generate(if...else), Verilator fails with:
Attached is a patch to show this in t_gen_if although I wasn't sure how to fix this. I considered only creating a new symbol table if we aren't in a generate but this breaks explicit signals, we could probably keep track of the last symbol table outside a generate and add implicit signals there but this would still show the incorrect line numbers for the variable.
Original Redmine Comment
It shouldn't have made the duplicate - it's a bug in the signal getting properly created under the module, but the symtable entry being under the generate rather than module.
Fixed in git for 3.800+.