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Support implicit signals in both branches of a generate(if..else) #201

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veripoolbot opened this issue Jan 11, 2010 · 2 comments
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Support implicit signals in both branches of a generate(if..else) #201

veripoolbot opened this issue Jan 11, 2010 · 2 comments
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@veripoolbot veripoolbot commented Jan 11, 2010


Author Name: Byron Bradley (@bbradley)
Original Redmine Issue: 201 from https://www.veripool.org
Original Date: 2010-01-11
Original Assignee: Wilson Snyder (@wsnyder)


If an implicit signal appears in both branches of a generate(if...else), Verilator fails with:

%Error: t/t_gen_if.v:28: Duplicate declaration of signal: imp
%Error: t/t_gen_if.v:22: ... Location of original declaration

Attached is a patch to show this in t_gen_if although I wasn't sure how to fix this. I considered only creating a new symbol table if we aren't in a generate but this breaks explicit signals, we could probably keep track of the last symbol table outside a generate and add implicit signals there but this would still show the incorrect line numbers for the variable.

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@veripoolbot veripoolbot commented Jan 11, 2010


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-01-11T17:36:21Z


It shouldn't have made the duplicate - it's a bug in the signal getting properly created under the module, but the symtable entry being under the generate rather than module.

Fixed in git for 3.800+.

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@veripoolbot veripoolbot commented Feb 7, 2010


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-02-07T12:41:59Z


In 3.800.

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