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Support multi-dimensional packed arrays of wires #206

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veripoolbot opened this issue Jan 19, 2010 · 1 comment
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Support multi-dimensional packed arrays of wires #206

veripoolbot opened this issue Jan 19, 2010 · 1 comment

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@veripoolbot veripoolbot commented Jan 19, 2010


Author Name: Byron Bradley (@bbradley)
Original Redmine Issue: 206 from https://www.veripool.org
Original Date: 2010-01-19
Original Assignee: Wilson Snyder (@wsnyder)


reg [1:0][1:0][1:0] works but wire [1:0][1:0][1:0] doesn't. A patch is attached to show this in t/t_mem_packed and it has been tested on another simulator.

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@veripoolbot veripoolbot commented Jan 25, 2010


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-01-25T12:52:45Z


Fixed in git; thanks for the testcase.

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