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Support assignment between packed arrays with different dimensions #207

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veripoolbot opened this issue Jan 19, 2010 · 1 comment
Closed

Support assignment between packed arrays with different dimensions #207

veripoolbot opened this issue Jan 19, 2010 · 1 comment

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@veripoolbot veripoolbot commented Jan 19, 2010


Author Name: Byron Bradley (@bbradley)
Original Redmine Issue: 207 from https://www.veripool.org
Original Date: 2010-01-19
Original Assignee: Byron Bradley (@bbradley)


Verilator doesn't support:

  logic [1023:0] data_conc;
  logic [31:0][31:0] data;
  assign data = data_conc;

Slice support in issue #170 comes very close to this. Remove the checks to detect it as an error and it just needs to figure out that it is packed and to set the bits in the Sel node on data_conc appropriately for each element in data. This probably needs a very strict check that the number of packed bits is equal on both sides.

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@veripoolbot veripoolbot commented Apr 2, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-02T03:22:05Z


Somewhere along the changes for packed array support this was fixed.

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