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In my love for parsers I have started playing around with a Verilator frontend for FIRRTL a while ago. It allows to directly feed chisel generated *.fir files into verilator without going through Verilog. The major advantage is that warnings and error messages can carry the scala fileline information at no extra cost. Constructing the AST from firrtl is pretty straightforward.
Do you think this would be a useful addition?