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loFIRRTL frontend #2084

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wallento opened this issue Dec 31, 2019 · 2 comments
Open

loFIRRTL frontend #2084

wallento opened this issue Dec 31, 2019 · 2 comments

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@wallento
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@wallento wallento commented Dec 31, 2019

In my love for parsers I have started playing around with a Verilator frontend for FIRRTL a while ago. It allows to directly feed chisel generated *.fir files into verilator without going through Verilog. The major advantage is that warnings and error messages can carry the scala fileline information at no extra cost. Constructing the AST from firrtl is pretty straightforward.

Do you think this would be a useful addition?

@wsnyder

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@wsnyder wsnyder commented Dec 31, 2019

For the FIRRTL nieve (e.g. me) can you point to some example files?

@omasanori

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@omasanori omasanori commented Jan 25, 2020

I am not a FIRRTL expert, but the samples/ directory of Treadle may be useful. Unfortunately, the spec lacks a precise definition of LoFIRRTL. Perhaps it does not matter since full FIRRTL is not so high-level compared to Verilog HDL, I guess? I missed "More pages" of preview, I apologize.

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