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verilator fails without providing examples: Unsupported: Blocked and non-blocking assignments to same variable #2170
In fact, this wire is always assigned in a non-blocking way, there are only few places.
How can I make verilator say where the blocking assignments are?
I found two lines which make Verilator think that there is a Delayed vs. NonDelayed assignment constraint violation.
Delayed assignment is just
But for NonDelayed assignment it shows the output of a mux:
The mux doesn't contain any NonDelayed assignments for its output:
Also, the problem only came up when this mux grew from 8 to 9 inputs, which is very strange. I think Verilator makes a mistake - there is a bug somewhere that makes Verilator think that there is a NonDelayed assignment there.