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Support behavioral PLLs/Events #223

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@veripoolbot

Author Name: Shankar Giri
Original Redmine Issue: 223 from https://www.veripool.org
Original Date: 2010-03-16


For fpga simulations, most RTL designs have primitives instantiated, like DDIO, PLL and so on. I would like to try and implement this.

From what I understand, these primitives are handled directly by the FPGA synthesis tools and that the verilog/vhdl code for what it actually implements is not available to the designer. FPGA vendors have simulation libraries for these primitives, but they are non-synthesizable.

Option 1: Write a synthesizable verilog code for the functionality taking into account information in the simulation model and the user guide. This could then be added to the file list during a verilator compilation. All these files would move into the verilator source tree to be included in the compilation when such a primitive instantiation is encountered.
Pros: No impact on verilator code. Just one more file for it.
Cons: Functional equivalency of the synthesizable verilog code needs to be validated thoroughly. Also not all primitives can be written this way (for eg. PLL, DLL. How do we handle it?)

Option 2: Describe these primitives directly in a C model so that they can directly be compiled and linked with the verilated code.
Pros: All primitives/cell libraries can be modelled in C/SystemC as synthesizability is not a constraint for C models.
Cons: Since these models are essentially part of the DUT, connecting these models to other parts of the DUT would have to be done internally through code. In other words, the DUT top level class has to instantiate our custom model as well and connect it properly.

I personally favour Option 2. There are two major steps to supporting this feature.

  1. Writing the C models for all primitives to be supported
  2. Framework to connect these models within the DUT.

Any other options of dealing with this, please do let me know.

Let me know your thoughts.

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