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Problem with clocks after commit e57d0047184 #265

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veripoolbot opened this issue Jun 14, 2010 · 3 comments
Closed

Problem with clocks after commit e57d0047184 #265

veripoolbot opened this issue Jun 14, 2010 · 3 comments

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@veripoolbot
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@veripoolbot veripoolbot commented Jun 14, 2010


Author Name: Byron Bradley (@bbradley)
Original Redmine Issue: 265 from https://www.veripool.org
Original Date: 2010-06-14
Original Assignee: Wilson Snyder (@wsnyder)


Commit e57d004 has caused one of our blocks to start failing all of the tests, reverting this commit makes them pass again. The problem seems to be related to clocks with multiple bits, i.e. our the top module contains:

input   logic [1:0] clk

and only one bit is being passed into a module:

someModule #(1) SOME_MODULE (.clk(clk[0]), ...)

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@veripoolbot veripoolbot commented Jun 22, 2010


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-06-22T00:41:57Z


I added the t/t_clk_2in_vec.pl to look for this bug, but it didn't turn up. Can you give more details of what the primary input looks like and what loads are on the bussed clock?

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@veripoolbot veripoolbot commented Jul 12, 2010


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-07-12T14:34:29Z


BTW this is still waiting on a testcase.

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@veripoolbot veripoolbot commented Dec 8, 2010


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-12-08T01:42:15Z


Please reopen with a test case if still failing, thanks.

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