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Problem with clocks after commit e57d0047184 #265
Commit e57d004 has caused one of our blocks to start failing all of the tests, reverting this commit makes them pass again. The problem seems to be related to clocks with multiple bits, i.e. our the top module contains:
and only one bit is being passed into a module:
Original Redmine Comment
I added the t/t_clk_2in_vec.pl to look for this bug, but it didn't turn up. Can you give more details of what the primary input looks like and what loads are on the bussed clock?