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"force bitvector" attribute #402

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veripoolbot opened this issue Oct 25, 2011 · 4 comments
Closed

"force bitvector" attribute #402

veripoolbot opened this issue Oct 25, 2011 · 4 comments

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@veripoolbot veripoolbot commented Oct 25, 2011


Author Name: Stefan Wallentowitz (@wallento)
Original Redmine Issue: 402 from https://www.veripool.org
Original Date: 2011-10-25


Hi,

I recently verilated our own Network-on-Chip implementation. For interaction between the system and the uut pins I created a transactor for SystemC TLM.
The problem, that came up, is that the interface has valid and ready signals. Their width is determined by the number of virtual channels which is a parameter to the module. Apparently I now have different module interfaces, namely a Mesh_v1 and Mesh_v2 version for one and two channels respectively. The interface ports are then of type bool and vluint32_t. As the transactor should be used with each version, I came up with the idea to force certain ports to be of type sc_bv. This also makes life easier in the transactor itself.
As the command line switches did not provide the required behavior (I want to keep other signals as vluint64_t), I created a simple patch, that you can please find attached.

Please comment on the patch, whether it makes sense in your opinion and how it may be improved.

Thanks in advance!

Bye,
Stefan

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@veripoolbot veripoolbot commented Oct 25, 2011


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-10-25T13:02:34Z


Nice work.

First, can you call it "verilator sc_bv", as it is similar to sc_clock?

Also, please update the bin/verilator file to document it (similar to sc_clock). You might note that sc_bv's are much slower than integers, so you're hurting performance every time you use this.

Finally, use it in a test, for example add a line using it to test_regress/t_var_pinsizes.v and test_regress/t_var_pinsizes.cpp. (Run it with test_regress/t_var_pinsizes.pl)

If these are acceptable can you post a new post and I'll apply it?

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@veripoolbot veripoolbot commented Oct 26, 2011


Original Redmine Comment
Author Name: Stefan Wallentowitz (@wallento)
Original Date: 2011-10-26T09:01:57Z


Thanks for the feedback.
Of course I changed the name, added documentation to bin/verilator and updated the respective regression files.

Hope I did everything right.

Bye,
Stefan

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@veripoolbot veripoolbot commented Oct 26, 2011


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-10-26T12:57:46Z


Looks good, thanks for patching! Moved a few lines to keep things sorted, but that's it.

In git towards 3.825.

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@veripoolbot veripoolbot commented Nov 27, 2011


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-11-27T15:44:55Z


In 3.830.

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