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Selecting Beyond Signal Bounds Is Possible #43

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veripoolbot opened this issue Nov 12, 2008 · 1 comment
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Selecting Beyond Signal Bounds Is Possible #43

veripoolbot opened this issue Nov 12, 2008 · 1 comment
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@veripoolbot veripoolbot commented Nov 12, 2008


Author Name: Lane Brooks
Original Redmine Issue: 43 from https://www.veripool.org
Original Date: 2008-11-12
Original Assignee: Wilson Snyder (@wsnyder)


I discovered in verilator that it is possible to select into a wire out side of its boundaries and the selection wraps. e.g.:

wire [1:0] in;
wire [1:0] out32 = in[3:2];
wire [1:0] out10 = in[1:0];

out10 and out32 come out equal. I am not sure what the verilog standard says, but I think I am used to this giving an error in other tools. I have attached a test that shows the behavior.

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@veripoolbot veripoolbot commented Nov 13, 2008


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2008-11-13T01:55:50Z


There was the t_select_bad_range test, but the difference and bug happens only when the MSB of the select range is binary all 1s and selects the entire width of the original signal. This causes the V3Width stage to optimize it before the warning sees it.

Fixed in git, will be in next release 3.682.

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