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Selecting Beyond Signal Bounds Is Possible #43
I discovered in verilator that it is possible to select into a wire out side of its boundaries and the selection wraps. e.g.:
wire [1:0] in;
out10 and out32 come out equal. I am not sure what the verilog standard says, but I think I am used to this giving an error in other tools. I have attached a test that shows the behavior.
Original Redmine Comment
There was the t_select_bad_range test, but the difference and bug happens only when the MSB of the select range is binary all 1s and selects the entire width of the original signal. This causes the V3Width stage to optimize it before the warning sees it.
Fixed in git, will be in next release 3.682.