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genvar declaration inside generate #461

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veripoolbot opened this issue Mar 22, 2012 · 5 comments
Closed

genvar declaration inside generate #461

veripoolbot opened this issue Mar 22, 2012 · 5 comments

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@veripoolbot veripoolbot commented Mar 22, 2012


Author Name: Alex Solomatnikov
Original Redmine Issue: 461 from https://www.veripool.org
Original Date: 2012-03-22
Original Assignee: Wilson Snyder (@wsnyder)


The following code in Altera's IP:

     generate
     genvar a;
     begin : unpack_odt_config // error!!!
         for (a=0; a<CFG_MEM_IF_CHIP; a=a+1)
         begin : unpack_odt_config_per_chip
...
         end
     end
     endgenerate


causes verilator error:

: syntax error, unexpected begin

VCS works fine.

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@veripoolbot veripoolbot commented Mar 22, 2012


Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2012-03-22T22:45:21Z


Obviously, low priority - the code can be easily fixed.

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@veripoolbot veripoolbot commented Mar 23, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-23T01:26:29Z


This is a bug in verilog-perl also, I will fix it there with high priority first as it is supposed to accept everything.

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@veripoolbot veripoolbot commented Mar 23, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-23T12:49:06Z


Verilog-Perl: Fixed in git towards 3.315.

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@veripoolbot veripoolbot commented Mar 23, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-23T12:50:24Z


Verilator fixed in git towards 3.833.

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@veripoolbot veripoolbot commented Apr 15, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-04-15T20:39:46Z


In 3.833.

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