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incorrect %Error: Selection index out of range #477

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veripoolbot opened this issue Apr 4, 2012 · 4 comments
Closed

incorrect %Error: Selection index out of range #477

veripoolbot opened this issue Apr 4, 2012 · 4 comments
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@veripoolbot veripoolbot commented Apr 4, 2012


Author Name: Alex Solomatnikov
Original Redmine Issue: 477 from https://www.veripool.org
Original Date: 2012-04-04
Original Assignee: Wilson Snyder (@wsnyder)


Test case:

module submod(
         rst_n,
         clk,
         rst_n_ext
);

parameter STAGES = 4;
parameter NUM_OUT = 1;

input   rst_n;
input   clk;
output  [NUM_OUT-1:0] rst_n_ext;

reg[STAGES+NUM_OUT-2:0] rst_reg;

generate
genvar i;
         for (i=0; i<STAGES+NUM_OUT-1; i=i+1)
         begin
                 always @(posedge clk or negedge rst_n)
                 begin
                         if (~rst_n)
                                 rst_reg[i] <= 1'b0;
                         else
                         begin
                                 if (i==0)
                                         rst_reg[i] <= 1'b1;
                                 else if (i < STAGES)
                                         rst_reg[i] <= rst_reg[i-1];
                                 else
                                         rst_reg[i] <= rst_reg[STAGES-2];
                                 
                         end
                 end
         end
endgenerate

         assign rst_n_ext = rst_reg[STAGES+NUM_OUT-2:STAGES-1];

endmodule


module test(
             input  rst_n,
             input  clk,
             output out
             );

    reg [4-1:0] rst1;

    submod  u1(
                 .rst_n        (rst_n),
                 .clk          (clk),
                 .rst_n_ext    (rst1)
         );
         defparam u1.STAGES  = 5; 
         defparam u1.NUM_OUT = 4;

    reg [1-1:0] rst2;

    submod  u2(
                 .rst_n        (rst_n),
                 .clk          (clk),
                 .rst_n_ext    (rst2)
         );
         defparam u2.STAGES = 5; 

endmodule

Error:

verilator -sp -Wno-fatal --top-module test test.v
%Error: test.v:29: Selection index out of range: 7:7 outside 4:0
%Error: test.v:29: Selection index out of range: 7:7 outside 4:0
%Error: Exiting due to 2 error(s)

Note that if any of two instantiations is commented out, there is no error.

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@veripoolbot veripoolbot commented Apr 4, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-04-04T02:35:49Z


Verilator doesn't realize that rst_reg[i-1] when the the loop has i=0 can not execute due to the if(i==0) condition before it. That's a pretty complicated thing to know so I'll probably make it a warning for now.

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@veripoolbot veripoolbot commented Apr 4, 2012


Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2012-04-04T03:30:40Z


Not sure why you mentioned if(i==0) condition. Verilator compiles without errors if there is only 1 instantiation, e.g.:

module test(
             input  rst_n,
             input  clk,
             output out
             );

    reg [4-1:0] rst1;

    submod  u1(
                 .rst_n        (rst_n),
                 .clk          (clk),
                 .rst_n_ext    (rst1)
         );
         defparam u1.STAGES  = 5; 
         defparam u1.NUM_OUT = 4;

endmodule

if() condition is still the same in this case.

I thought it is a scope issue, i.e. in different pieces of analysis pick different values of parameters for the same instantiation.

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@veripoolbot veripoolbot commented Apr 5, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-04-05T01:56:21Z


If you comment out the u1 instantiation you will see it fails for u2 only. This is because u1 does have an index [7] so there's nothing to warn about.

Anyhow added SELRANGE warning in git towards 3.833.

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@veripoolbot veripoolbot commented Apr 15, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-04-15T20:38:50Z


In 3.833.

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