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Support SystemVerilog string initializations #506
Author Name: Alex Solomatnikov
I tried to compile Altera's DDR3 controller and testbench with Micron's DDR3 DRAM model (Altera's DRAM model does not compile because of structs).
Verilator completes without errors, however, generated code does not compile with gcc:
The first error is on line with VL_SFORMAT_X().
It seems related to #� - I commented out string message declaration to get around #�, which I guess makes the code incorrect, although verilator and VCS do not complain.
Original Redmine Comment
It seems verilator does not support strings in general - I commented out that string initialization and it still generates the same incorrect code, although it does not say anything.