Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Support SystemVerilog string initializations #506

Closed
veripoolbot opened this issue May 5, 2012 · 5 comments
Closed

Support SystemVerilog string initializations #506

veripoolbot opened this issue May 5, 2012 · 5 comments

Comments

@veripoolbot
Copy link

@veripoolbot veripoolbot commented May 5, 2012


Author Name: Alex Solomatnikov
Original Redmine Issue: 506 from https://www.veripool.org
Original Date: 2012-05-05


I tried to compile Altera's DDR3 controller and testbench with Micron's DDR3 DRAM model (Altera's DRAM model does not compile because of structs).

Verilator completes without errors, however, generated code does not compile with gcc:

g++44  -I. -MMD -I.../verilator/include -I.../verilator/include/vltstd -DVL_PRINTF=printf -DVM_TRACE=0 -DVM_COVERAGE=0 -c -o Vddr3_ctlr_m0_q11_1sp2_example_sim__ALLcls.o Vddr3_ctlr_m0_q11_1sp2_example_sim__ALLcls.cpp
In file included from Vddr3_ctlr_m0_q11_1sp2_example_sim__ALLcls.cpp:2:
Vddr3_ctlr_m0_q11_1sp2_example_sim.cpp: In static member function ‘static void Vddr3_ctlr_m0_q11_1sp2_example_sim::_initial__TOP(Vddr3_ctlr_m0_q11_1sp2_example_sim__Syms*)’:
Vddr3_ctlr_m0_q11_1sp2_example_sim.cpp:25917: error: ‘struct Vddr3_ctlr_m0_q11_1sp2_example_sim’ has no member named ‘message’
Vddr3_ctlr_m0_q11_1sp2_example_sim.cpp:25920: error: ‘struct Vddr3_ctlr_m0_q11_1sp2_example_sim’ has no member named ‘message’
Vddr3_ctlr_m0_q11_1sp2_example_sim.cpp:25922: warning: cannot pass objects of non-POD type ‘struct std::string’ through ‘...’; call will abort at runtime
...

generate code:

     // INITIAL at ..//submodules//./..//submodules/altera_avalon_clock_source.sv:76 
     // Function: ___05Fhello at ..//submodules//./..//submodules/altera_avalon_clock_source.sv:77 
     VL_SFORMAT_X(64,vlTOPp->message,"%Nv.pll_ref_clk: - Hello from altera_clock_source.", 
                  vlSymsp->name()); 
     // Function: print at ..//submodules//./..//submodules/altera_avalon_clock_source.sv:40 
     __Vtask_print__1__message = vlTOPp->message; 
     VL_WRITEF("%20t:    INFO: %s\n",64,VL_TIME_Q(), 
               64,__Vtask_print__1__message); 

The first error is on line with VL_SFORMAT_X().

Source code:

    import verbosity_pkg::*; 
 
    localparam HALF_CLOCK_PERIOD   = 1000.000000/CLOCK_RATE/2; // half clock period in ns 
     
    logic clk = 1'b0; 
 
//   string message   = "*uninitialized*"; 
    bit    run_state = 1'b1; 
 
    function automatic void __hello(); 
       $sformat(message, "%m: - Hello from altera_clock_source."); 
       print(VERBOSITY_INFO, message);             
       $sformat(message, "%m: -   $Revision: #1 $"); 
       print(VERBOSITY_INFO, message);             
       $sformat(message, "%m: -   $Date: 2011/11/10 $"); 
       print(VERBOSITY_INFO, message); 
       $sformat(message, "%m: -   CLOCK_RATE = %0d", CLOCK_RATE);       
       print(VERBOSITY_INFO, message); 
       print_divider(VERBOSITY_INFO);       
    endfunction 
...
    initial begin 
       __hello(); 
    end 

It seems related to #� - I commented out string message declaration to get around #�, which I guess makes the code incorrect, although verilator and VCS do not complain.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented May 5, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-05-05T11:40:58Z


Verilator currently only supports 'string' as part of a DPI export/import. It should at least throw an error, if not support this.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented May 5, 2012


Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2012-05-05T15:39:22Z


It seems verilator does not support strings in general - I commented out that string initialization and it still generates the same incorrect code, although it does not say anything.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Nov 28, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-11-28T20:04:04Z


Git towards 3.867 contains more robust string handling. Please give it a try and if there are still issues post a test, thanks.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Dec 20, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-12-20T21:53:55Z


In 3.868.

@veripoolbot

This comment has been minimized.

Copy link
Author

@veripoolbot veripoolbot commented Dec 21, 2014


Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2014-12-21T00:09:50Z


It's hard to re-produce this issue - the environment, RTL, etc. evolved a lot over 2 years.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Linked pull requests

Successfully merging a pull request may close this issue.

None yet
1 participant
You can’t perform that action at this time.