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Missing width warning when part of a bus is compared #533

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veripoolbot opened this issue Jul 20, 2012 · 4 comments
Open

Missing width warning when part of a bus is compared #533

veripoolbot opened this issue Jul 20, 2012 · 4 comments

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@veripoolbot veripoolbot commented Jul 20, 2012


Author Name: Chandan Egbert
Original Redmine Issue: 533 from https://www.veripool.org
Original Date: 2012-07-20


Verilator generates incorrect code for the comparison

~a[m:0] == 0

where the total width of "a" is larger than m. The comparison in the following example

module select_invert(input logic clk, input logic [15:0] a);
     always @(posedge clk) begin
         if ((~a[5:0] == 0) == 0) begin
             $write("[%0t] %%Error: t_select_invert: failed\n", $time);
             $stop;
         end
     end
endmodule

should produce the value 1 when a is 0xffff. However, it produces the value 0.

An example in the verilator test_regress style is attached.

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@veripoolbot veripoolbot commented Jul 20, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-07-20T10:29:03Z


Thanks for the good test, however I'm not sure why you think the answer should be 1, as VCS, NC and Verilator all agree the answer is 0.

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@veripoolbot veripoolbot commented Jul 20, 2012


Original Redmine Comment
Author Name: Chandan Egbert
Original Date: 2012-07-20T14:56:43Z


If a = 16'hffff, a[5:0] would be 6'h3f. Inverting this should give 0. comparing this with 0 should give TRUE. However I get FALSE. Looking at the generated C code, I see that the verilog expression

~a[5:0] == 0

which should evaluate to TRUE

has been translated into

(0 == (~ (0x3f & (IData)(vlTOPp->v__DOT__val))))

which evaluates to FALSE.

Am I missing something here?

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@veripoolbot veripoolbot commented Jul 20, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-07-20T15:17:10Z


0 is 32 bits wide, not 6 bits. If you compare with 6'h0 you'll get what you expect.

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@veripoolbot veripoolbot commented Jul 20, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-07-20T15:23:30Z


Actually there should be a WIDTH warning here to tell people what's odd.

Note also your test needs to compare only when a==40'h7fffffff as otherwise there's a time 0 race.

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