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Support associative arrays #544

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veripoolbot opened this issue Aug 9, 2012 · 9 comments
Closed

Support associative arrays #544

veripoolbot opened this issue Aug 9, 2012 · 9 comments

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@veripoolbot veripoolbot commented Aug 9, 2012


Author Name: Alex Solomatnikov
Original Redmine Issue: 544 from https://www.veripool.org


Obviously not synthesizable but useful for testbenches and behavioral models.

Example:

bit [MEM_DQ_WIDTH - 1:0] mem_data[*]

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@veripoolbot veripoolbot commented Aug 9, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-08-09T01:58:53Z


Unfortunately not high priority for my usage, and requires moderate work as it's a dynamic construct. Perhaps you or someone else will be interested in implementing it.

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@veripoolbot veripoolbot commented Aug 10, 2012


Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2012-08-10T06:11:32Z


Could you explain a little bit what needs to be done for this? I am assuming backend implementation would use an existing map, e.g. STL map?

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@veripoolbot veripoolbot commented Aug 10, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-08-10T23:56:05Z


It's not too hard, just a lot of effort on details. First there's the parsing, and creating related Ast node types which is pretty easy. The big thing is all present internal analysis assumes the entire state of the model is available for static analysis, that will have to be bypassed. (Not allowing <= assignments would simplify.) Then the actual implementation which can yes be a map, though the key type needs to allow arbitrary width numbers. This needs to be implemented (as most things are) in both verilator for static analysis and in the runtime. Finally there's how to waveform trace something like this.

If you only have a few, you can easily make a dpi function to do your lookup or faster something like this instead (untested): Note that using `systemc stuff disables some optimizations.

`systemc_header
#include <map>
`systemc_interface
map<vluint64_t,vluint64_t> mem_data;
`verilog

...
// mem_data[y] = x
$c("mem_data[",y,"]=",x);

// x = mem_data[y]
x = $c64("mem_data[",y,"]");

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@veripoolbot veripoolbot commented Aug 10, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-08-10T23:57:15Z


Fixed lookup line to "mem_data[",y,"]".

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@veripoolbot veripoolbot commented Dec 4, 2013


Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2013-12-04T18:33:25Z


Another example from behavioral AXI slave model:

int unsigned addr;
assign addr = mem_address;

generate
  for(mem_byte_index=0; mem_byte_index<= (C_S_AXI_DATA_WIDTH/8)-1; mem_byte_index=mem_byte_index+1) begin:BYTE_BRAM_GEN
     wire [(C_S_AXI_DATA_WIDTH/8)-1:0] data_in ;
     reg  [(C_S_AXI_DATA_WIDTH/8)-1:0] byte_ram [int unsigned];
     integer  j;
  
     //assigning 8 bit data
     assign data_in  = S_AXI_WDATA[(mem_byte_index*8+7) -: 8];
  
     always @( posedge S_AXI_ACLK ) begin
       if (mem_wren && S_AXI_WSTRB[mem_byte_index])  begin
         byte_ram[addr] <= data_in;
       end
       if (mem_rden) begin
          if (byte_ram.exists(addr)) begin
             mem_data_out[(mem_byte_index*8+7) -: 8] <= byte_ram[addr];
          end
          else begin
             mem_data_out[(mem_byte_index*8+7) -: 8] <= 0;
          end
       end
     end
  end
endgenerate

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@veripoolbot veripoolbot commented Jan 23, 2019


Original Redmine Comment
Author Name: Aliaksei Chapyzhenka
Original Date: 2019-01-23T05:17:40Z


Looks like a useful feature. Have anybody made any progress in making associative arrays work?

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@veripoolbot veripoolbot commented Jan 25, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-01-25T00:20:17Z


Patches still wanted/welcome.

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@veripoolbot veripoolbot commented Dec 1, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-12-01T16:54:37Z


Associative array support for general types, excluding [*] and pattern assignment, is in git for eventual 4.024 release.

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@veripoolbot veripoolbot commented Dec 8, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-12-08T13:12:35Z


In 4.024.

For additional support related to this please file new bug.

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