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generate/endgenerate should not be optional in Verilog 2001 #576
@generate@/@endgenerate@ are required in Verilog 2001, but not in 2005. So the following code should generate an error with Verilog 2001.
// This is a Verilog 2005 test (generate/endgenerate omitted).
However this code compiles with Verilog 2001 set as the language (@--language 1364-2001@).
It's not terribly important. I found it trying to construct a test of new language extension options. Added here for the record.