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generate/endgenerate should not be optional in Verilog 2001 #576

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veripoolbot opened this issue Nov 7, 2012 · 1 comment
Closed

generate/endgenerate should not be optional in Verilog 2001 #576

veripoolbot opened this issue Nov 7, 2012 · 1 comment

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@veripoolbot veripoolbot commented Nov 7, 2012


Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 576 from https://www.veripool.org
Original Date: 2012-11-07


@generate@/@endgenerate@ are required in Verilog 2001, but not in 2005. So the following code should generate an error with Verilog 2001.

// This is a Verilog 2005 test (generate/endgenerate omitted).
genvar i;
for (i=0; i<2; i=i+1) begin
always @(posedge clk) begin
res[i:i] <= in;
end
end

However this code compiles with Verilog 2001 set as the language (@--language 1364-2001@).

It's not terribly important. I found it trying to construct a test of new language extension options. Added here for the record.

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@veripoolbot veripoolbot commented Nov 29, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-11-29T02:40:32Z


Closing due to age; not easy to fix in current parser, and Verilog 2001 is getting pretty old.

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