Join GitHub today
GitHub is home to over 40 million developers working together to host and review code, manage projects, and build software together.Sign up
Short-circuit bitwise-AND and bitwise-OR (Verilog only) #578
The earlier patch for Issue 413 (http://www.veripool.org/issues/413-Verilator-generate-conditional-with-short-circuited-local-expression) implemented short-circuiting in line with the SystemVerilog IEEE 1800-2005 standard, which permits this only for logical OR, logical AND and the conditional operator. Verilog is more permissive, allowing short-circuiting of other operators, notably bitwise-AND and bitwise-OR (the former being used in the Verilog 2001 standard as an example).
This patch implements Verilog short-circuiting for bitwise-AND and bitwise-OR for source files, whose language type is Verilog 1995, Verilog 2001 or Verilog 2005. This can be set using @--language@/@--default-language@ or by the various file extension options, such as @+verilog2001ext+@. This patch builds on the changes in the patch to fix Issue 532 (http://www.veripool.org/issues/532).
Note. I don't have a copy of the Verilog 2005 standard, to check that this still permits such short-circuiting. It is trivial to change the function @isVerilog()@ in @V3Const.cpp@ to restrict to just Verilog 1995 and Verilog 2001 if necessary.
All existing regression tests still pass. Please pull the patch from the verilog-short-circuit branch at https://github.com/jeremybennett/verilator. Note this must be applied after the patch to Issue 532.
Original Redmine Comment
The language in 1394 says "the entire expression need not be evaluated", this is not a shall/must as is in the recent standard. Furthermore I ran the test on NC-Verilog and it does NOT seem to short circuit verilog 2001 | or &.
Therefore I believe the existing implementation is compliant, and I'm reluctant to have behavior that is different for other language versions if it can at all be avoided.