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Bit select from 1-bit parameter causes error #603

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veripoolbot opened this issue Jan 16, 2013 · 2 comments
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Bit select from 1-bit parameter causes error #603

veripoolbot opened this issue Jan 16, 2013 · 2 comments

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@veripoolbot veripoolbot commented Jan 16, 2013


Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 603 from https://www.veripool.org
Original Date: 2013-01-16
Original Assignee: Wilson Snyder (@wsnyder)


The following code causes a Verilator error.

    parameter a = 1'b0;
    wire  b = a[0];

The error is:

%Error: t/t_param_bit_sel.v:19: Illegal bit or array select; type does not have a bit range, or bad dimension: type is bit

It seems that Verilator assumes that a 1-bit wide parameter must be a scalar, rather than a 1-bit wide vector. Other simulators (e.g. VCS, Icarus) do not make this assumption and pass this code cleanly.

Please pull a test case from branch param-bit-sel at git@github.com:jeremybennett/verilator.git

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@veripoolbot veripoolbot commented Jan 17, 2013


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-01-17T01:59:03Z


Very surprising as "wire foo" isn't allowed to get "foo[ 0 ]". parameters inherit the type of the assignment, but the type is a bit. Anyhow.

Fixed in git towards 3.845.

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@veripoolbot veripoolbot commented Feb 5, 2013


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-02-05T03:22:07Z


In 3.845.

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