-x-initial-edge breaks with logic bug fix #604
Comments
Original Redmine Comment #�_initial_edge branch contains the necessary edits, as another test needed a fixup too. |
Original Redmine Comment The test for when to implement --x-initial-edge in EmitCImp::emitVarResets() in V3EmitC.cpp was wrong.
Please pull a corrected version (as a sub-branch of #�_initial_edge) from branch x-initial-edge at git@github.com:jeremybennett/verilator.git |
Original Redmine Comment Thanks for the quick fix. I added a || zeroit as otherwise the t_var_types test correctly noticed that a 2-state type wasn't zero initialized. This should be still compatible with other simulators as a two-state which inits to zero will NOT trigger a negedge, it's the X->0 that does. Applied. |
Author Name: Wilson Snyder (@wsnyder)
Original Redmine Issue: 604 from https://www.veripool.org
Original Date: 2013-01-17
Original Assignee: Jeremy Bennett (@jeremybennett)
Part of the fix for #� uncovered a bug I had in V3AstNodes.cpp. The git head now includes these lines:
The use of ::BIT here should have been kwd. This bug means some logic types were mis-converted to bit types.
However fixing this breaks the t_initial_edge test.
Can you look into this?
The text was updated successfully, but these errors were encountered: