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Verilator internal fault #607

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veripoolbot opened this issue Jan 22, 2013 · 4 comments
Closed

Verilator internal fault #607

veripoolbot opened this issue Jan 22, 2013 · 4 comments
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@veripoolbot veripoolbot commented Jan 22, 2013


Author Name: Jie Xu (@jiexu)
Original Redmine Issue: 607 from https://www.veripool.org
Original Date: 2013-01-22
Original Assignee: Wilson Snyder (@wsnyder)


Adding two lines to t/t_param_mem_attr.v test in verilator test_regress folder causes Verilator generating an internal fault.

module t (/*AUTOARG*/
    // Inputs
    clk
    );
    input clk;
    wire [71:0] ctrl;
    wire [7:0] cl;                       // this line is added 

    memory #(.words(72)) i_memory (.clk (clk));

    assign ctrl = i_memory.mem[0];
    assign cl   = i_memory.mem[0][7:0];  // and this line
endmodule


// memory module, which is used with parameter
module memory (clk);
    input clk;

    parameter words = 16384, bits = 72;

    reg [bits-1 :0] mem[words-1 : 0];

endmodule


However, vcs passes the same test.

This issue may relate to issue [[http://www.veripool.org/issues/583]].

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@veripoolbot veripoolbot commented Jan 26, 2013


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-01-26T02:27:41Z


Fixed in git towards 3.845.

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@veripoolbot veripoolbot commented Jan 28, 2013


Original Redmine Comment
Author Name: Jie Xu (@jiexu)
Original Date: 2013-01-28T07:15:20Z


Hi Wilson,

Has the change for this issue been taken to git source? I can not get any new commit from verilator git source.

Thanks for the fixing.

Jie

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@veripoolbot veripoolbot commented Jan 28, 2013


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-01-28T12:28:06Z


Sorry, forgot to 'git push' try again.

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@veripoolbot veripoolbot commented Feb 5, 2013


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-02-05T03:22:25Z


In 3.845.

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