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error on array port connection #609

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veripoolbot opened this issue Feb 1, 2013 · 4 comments
Closed

error on array port connection #609

veripoolbot opened this issue Feb 1, 2013 · 4 comments
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@veripoolbot veripoolbot commented Feb 1, 2013


Author Name: Alex Solomatnikov
Original Redmine Issue: 609 from https://www.veripool.org
Original Date: 2013-02-01
Original Assignee: Wilson Snyder (@wsnyder)


RTL:

module cache
  (
    output cache_tag_t        tag_out  [`CACHE_WAYS-1:0], // Tags from all ways
...
endmodule

    cache  cache(
                          .tag_out             (tag_cache_pipe  [`CACHE_WAYS-1:0]),         

Error:

%Error: ...: Illegal port connection tag_out, port is not an array expression is an array

Not clear what the message is supposed to mean.

Used to compile in 3.842.

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@veripoolbot veripoolbot commented Feb 1, 2013


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-02-01T22:40:05Z


Sorry, but I really need to get complete examples in the format like test_regress/t/t_EXAMPLE.v as described in the manual.

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@veripoolbot veripoolbot commented Feb 2, 2013


Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2013-02-02T01:51:21Z


Here is modified test from regress:

module t (/*AUTOARG*/
    // Inputs
    clk
    );
    input clk;

    logic [6-1:0] foo[4-1:0];

    dut #(.W(6),
          .D(4)) udut(.clk(clk),
                      .foo(foo[4-1:0]));
endmodule

module dut
     #(parameter W = 1,
       parameter D = 1)
     (input logic clk,
      input logic [W-1:0] foo[D-1:0]);

     genvar i, j;
     generate
        for (j = 0; j < D; j++) begin
           for (i = 0; i < W; i++) begin
              suba ua(.clk(clk), .foo(foo[j][i]));
           end
        end
     endgenerate
endmodule

module suba
  (input logic clk,
    input logic foo);

    always @(posedge clk) begin
       $write("*-* All Finished *-*\n");
       $finish;
    end
endmodule

The error:

./verilator --cc --top-module t t_bug609.v
%Error: t_bug609.v:18: Illegal port connection foo, port is not an array expression is an array.
%Error: Exiting due to 1 error(s)

Earlier version:

/tools/verilator/verilator-3.842/bin/verilator --cc --top-module t t_bug609.v

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@veripoolbot veripoolbot commented Feb 3, 2013


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-02-03T18:22:01Z


The obvious fix for this breaks several tests so will take a bit longer; current support for slices which this is isn't very good, it's only that this was a complete slice that it happened to work with the old version. For now just remove the [4-1:0] from the port declaration.

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@veripoolbot veripoolbot commented Feb 5, 2013


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-02-05T03:19:07Z


Fixed in 3.845.

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