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SystemVerilog operator overloading (bind construct) #633
Author Name: Yves Mathieu
Operator overloading is supported by SystemVerilog standard (chap 11.11 in 1800_2012 version).
This feature is already supported by CAD tools for many years for VHDL language, furthermore the recently standardised VHDL fixed-point and floating point (synthesizable) packages use operator overloading.
I wonder what would be the cost of supporting this feature:
Original Redmine Comment
Generic classes would need to be supported first, followed by many other things that synthesis/simulators DO support. So unless you are willing to put some good time in to help it along I don't expect attention would go towards this for several years.