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SystemVerilog operator overloading (bind construct) #633

veripoolbot opened this issue Mar 13, 2013 · 1 comment

SystemVerilog operator overloading (bind construct) #633

veripoolbot opened this issue Mar 13, 2013 · 1 comment


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@veripoolbot veripoolbot commented Mar 13, 2013

Author Name: Yves Mathieu
Original Redmine Issue: 633 from
Original Date: 2013-03-13

Operator overloading is supported by SystemVerilog standard (chap 11.11 in 1800_2012 version).
To my knowledge no commercial simulation or synthesis tool has any support for this feature.

This feature is already supported by CAD tools for many years for VHDL language, furthermore the recently standardised VHDL fixed-point and floating point (synthesizable) packages use operator overloading.

I wonder what would be the cost of supporting this feature:
-1 - for simulation
-2 - for synthesis : Verilator could be used as a translator from "SystemVerilog" to "SystemVerilog" to target synthesis tools that do not support this feature

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@veripoolbot veripoolbot commented Mar 16, 2013

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-03-16T00:32:20Z

Generic classes would need to be supported first, followed by many other things that synthesis/simulators DO support. So unless you are willing to put some good time in to help it along I don't expect attention would go towards this for several years.

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