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Clock gated signals not synchronised if used as a logical input #662

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veripoolbot opened this issue Jun 28, 2013 · 1 comment
Open

Clock gated signals not synchronised if used as a logical input #662

veripoolbot opened this issue Jun 28, 2013 · 1 comment

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@veripoolbot veripoolbot commented Jun 28, 2013


Author Name: Charlie Brej
Original Redmine Issue: 662 from https://www.veripool.org
Original Date: 2013-06-28


When a clock gated signal is used as a logical input it loses it's synchronization with the input clock. This is rarely a problem as the clock is only sensed with edge sensitive always statements, but if it is ever an input to logic it becomes unsynchronized again.

Test case attached. Removing the "$display("Clock is %d", clk2);" line makes the test pass again.

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@veripoolbot veripoolbot commented Jul 3, 2013


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-07-03T00:39:26Z


Haven't had a chance to look at this yet, sorry.

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