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Segmentation fault with variable of parameterized interface #692

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veripoolbot opened this issue Oct 30, 2013 · 6 comments
Closed

Segmentation fault with variable of parameterized interface #692

veripoolbot opened this issue Oct 30, 2013 · 6 comments

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@veripoolbot veripoolbot commented Oct 30, 2013


Author Name: Jie Xu (@jiexu)
Original Redmine Issue: 692 from https://www.veripool.org
Original Date: 2013-10-30
Original Assignee: Jie Xu (@jiexu)


Compiling the following code causes Verilator ending with Segmentation fault:

module t (/*AUTOARG*/
    // Inputs
    clk
    );
    input  wire       clk;

    wire [31:0] result;
    test_if  #(.id(3)) s();
    sub_test U_SUB_TEST(s.a.b, result);  // the line causing error

endmodule : t


// ---------------------------------------------------------------------------
// sub-module
// ---------------------------------------------------------------------------
module sub_test(
         input [31:0] b,
         output [31:0] c
         );

assign c = b;
endmodule

// ---------------------------------------------------------------------------
// interface
// ---------------------------------------------------------------------------

interface test_if
     #(parameter id = 0)
     ();

typedef struct packed {
     logic a;
     logic [31:0] b;
} aType;

 aType a;


typedef struct packed {
     logic c;
     logic [31:0] d;
} bType;

 bType b;


 modport master (input a, output b);

endinterface


The test case in Verilator regression format can be pulled here: https://github.com/jiexu/verilator paraInterface

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@veripoolbot veripoolbot commented Oct 31, 2013


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-10-31T03:28:25Z


This is a problem with the dead code eliminator. With --debug I fixed it to at least crash with an internal error, the real fix will take a bit of work, please stay tuned; if you want a work around use the interface with default parameters elsewhere or change the default parameters to match those needed in the instance.

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@veripoolbot veripoolbot commented Nov 11, 2013


Original Redmine Comment
Author Name: Jie Xu (@jiexu)
Original Date: 2013-11-11T15:33:11Z


This issue is not particular for parameterized interface. Parameterized module will also fail in this case.

An alternative workaround by using a temporary variable:

    test_if  #(.id(3)) s();
    logic [31:0] tmp;
    assign tmp = s.a.b;                // added variable
    sub_test U_SUB_TEST(tmp, result);  // no error now

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@veripoolbot veripoolbot commented May 28, 2014


Original Redmine Comment
Author Name: Jie Xu (@jiexu)
Original Date: 2014-05-28T08:40:25Z


Based on the observation that it works in AstAssignW, I come up the following patch for fixing this issue. Initial regression test seems OK.

diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 2429561..c4e1dca 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -1450,6 +1450,7 @@ private:
      }
      virtual void visit(AstPin* nodep, AstNUser*) {
         // Pin: Link to submodule's port
+       nodep->iterateChildren(*this);
         checkNoDot(nodep);
         if (!nodep->modVarp()) {
             if (!m_pinSymp) nodep->v3fatalSrc("Pin not under cell?\n");
@@ -1475,7 +1476,6 @@ private:
                     refp->user5p(nodep);
                 }
             }
-           nodep->iterateChildren(*this);
         }
         // Early return() above when deleted
      }

Please have a look.

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@veripoolbot veripoolbot commented May 28, 2014


Original Redmine Comment
Author Name: Jie Xu (@jiexu)
Original Date: 2014-05-28T09:20:18Z


FYI, the reason I get back to this issue is we have some incorrect simulation results from Verilator. It turns out that Verilator doesn't handle the pin assignment (involving an expression of interface members) correctly. The above patch fixes this issue as well.

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@veripoolbot veripoolbot commented May 28, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-28T11:35:07Z


Love patches!

Fix looks right on, thanks for debugging.

Fixed in git towards 3.861.

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@veripoolbot veripoolbot commented Jun 11, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-06-11T00:56:44Z


In 3.862.

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