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Crash with port = syntax error #716

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veripoolbot opened this issue Feb 14, 2014 · 3 comments
Closed

Crash with port = syntax error #716

veripoolbot opened this issue Feb 14, 2014 · 3 comments
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@veripoolbot veripoolbot commented Feb 14, 2014


Author Name: Lane Brooks
Original Redmine Issue: 716 from https://www.veripool.org
Original Date: 2014-02-14
Original Assignee: Wilson Snyder (@wsnyder)


I discovered that adding an '=' symbol to a verilog port causes verilator_bin to %Error without a useful message. Following is an example. I am not using the latest version of verilator, so I am not sure if it is has already been fixed.

module port_test
  (
    input A=asdf,
    input B
    );
endmodule

Sorry for not creating a test and submitting it that way.

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@veripoolbot veripoolbot commented Feb 14, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-02-14T20:22:21Z


Thanks, I'll see what's up.

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@veripoolbot veripoolbot commented Mar 8, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-03-08T17:27:38Z


Fixed in git towards 3.856.

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@veripoolbot veripoolbot commented Mar 12, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-03-12T00:05:59Z


In 3.856.

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