Verilator bug in extending $signed

@cliffordwolf

Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 733 from https://www.veripool.org
Original Date: 2014-04-06

The following module should output 4'b1111 but Verilator GIT 14fcfd8 outputs 4'b0001 instead.

module issue_005(y);
  wire [3:0] a;
  output [3:0] y;
  assign a = 4'b0010;
  assign y = $signed(|a);
endmodule

A self-contained test can be found here:

@wsnyder

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-07T02:02:04Z

This was caused by the fix for #�, and did not exist in previous versions.

Please see notes in #�.

@wsnyder

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-08T01:34:08Z

Fixed in git; never in release.

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