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Strange Verilator behavior with power, signdness and more #735

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veripoolbot opened this issue Apr 8, 2014 · 2 comments
Closed

Strange Verilator behavior with power, signdness and more #735

veripoolbot opened this issue Apr 8, 2014 · 2 comments

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@veripoolbot veripoolbot commented Apr 8, 2014


Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 735 from https://www.veripool.org
Original Date: 2014-04-08


The following module should output 0x00000000 for a=0 and 0x010000ff for a=1. But Verilator GIT 5c39420 outputs 0xffffffff for a=1 instead.

module test004(a, y);
  input a;
  output [31:0] y;

  wire [7:0] y0;
  wire [7:0] y1;
  wire [7:0] y2;
  wire [7:0] y3;
  assign y = {y0,y1,y2,y3};

  localparam [7:0] v0 = +8'sd1 ** -8'sd2;
  localparam [7:0] v1 = +8'sd2 ** -8'sd2;
  localparam [7:0] v2 = -8'sd2 ** -8'sd3;
  localparam [7:0] v3 = -8'sd1 ** -8'sd3;
  localparam [7:0] zero = 0;

  assign y0 = a ? v0 : zero;
  assign y1 = a ? v1 : zero;
  assign y2 = a ? v2 : zero;
  assign y3 = a ? v3 : zero;
endmodule

Interestingly the output value for y3 is correct, but setting y3 to a constant value (or otherwise removing the calculation for y3) makes the problem go away. Replacing a with 1 in the assign statements also does make the problem disappear.

Self-contained test case:

http://svn.clifford.at/handicraft/2014/verilatortest/test004.v

http://svn.clifford.at/handicraft/2014/verilatortest/test004.cc

http://svn.clifford.at/handicraft/2014/verilatortest/test004.sh

@veripoolbot
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@veripoolbot veripoolbot commented Apr 9, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-09T00:29:25Z


Yes that was weird, the number library had "hidden state" that confused the generated C code.

Fixed in git towards 3.857.

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@veripoolbot
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@veripoolbot veripoolbot commented May 11, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-11T21:08:14Z


In 3.860.

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