Verilator bug in signed/unsigned expression eval

[veripoolbot]

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Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 737 from https://www.veripool.org
Original Date: 2014-04-09
Original Assignee: Wilson Snyder (@wsnyder)

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The term "(p1 + p2)" below is part of an unsigned expression and thus should
be zero-extended. Verilator fb4928b however performs signed bit extension
and thus returns an incorrect result.

module issue_035(a, y);
  input [3:0] a;
  output [5:0] y;

  localparam signed [3:0] p1 = 4'b1000;
  localparam signed [3:0] p2 = 0;
  assign y = a + (p1 + p2);
endmodule

Crosscheck: Vivado 2013.4, XST 14.7, Quartus 13.1, Xsim 2013.4 and Modelsim
10.1d implement this correctly.

Self-contained test case:

http://svn.clifford.at/handicraft/2014/verilatortest/test006.v

http://svn.clifford.at/handicraft/2014/verilatortest/test006.cc

http://svn.clifford.at/handicraft/2014/verilatortest/test006.sh

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-15T23:38:34Z

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Stay tuned. I'm using this bug and the others as motivation to audit and cleanup all of the WIDTH related fixup code.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-30T02:03:26Z

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Fixed in git towards 3.857.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-11T21:09:23Z

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In 3.860.