Verilator Internal Error for shift by undef value

[veripoolbot]

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Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 760 from https://www.veripool.org
Original Date: 2014-05-04
Original Assignee: Wilson Snyder (@wsnyder)

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Verilator 4a58e85 creates the following error:
"%Error: Internal Error: ../V3Number.cpp:521: toUInt with 4-state 4'bxxxx"

  input [3:0] a;
  output [3:0] y;
  assign y = a >>> 4'bx;
endmodule

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-04T12:53:42Z

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Fixed in git towards 3.857.

I fixed this as it is easy, but in general verilator is only a two state simulator with very limited X/Z handling, so would prefer focus on non-X/Z.

[veripoolbot]

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Original Redmine Comment
Author Name: Clifford Wolf (@cliffordwolf)
Original Date: 2014-05-05T11:04:36Z

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Wilson Snyder wrote:

I fixed this as it is easy, but in general verilator is only a two state simulator with very limited X/Z handling, so would prefer focus on non-X/Z.

I already have a hack in place that ignores the verilator output bits that are set to X by the Yosys evaluator. Besides that it is hard to 'focus' on any specific kind of bug. For example I extracted this issue from the following test case: http://pastebin.com/UNWAmA0w (bug in y6 because p15 is undef). When generating test cases like that it is hard to avoid certain corner cases while at the same time trying to cover all the other corner cases.. ;)

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-11T21:11:25Z

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In 3.860.