Yet another Verilator shift bug

[veripoolbot]

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Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 763 from https://www.veripool.org
Original Date: 2014-05-10
Original Assignee: Wilson Snyder (@wsnyder)

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This should effectively be y=0, but verilator 1f56312 evaluates y=a instead.

  input [2:0] a;
  output [3:0] y;
  assign y = (a >> 2'b11) >> 1;
endmodule

Self-contained test case:

http://svn.clifford.at/handicraft/2014/verilatortest/test012.v

http://svn.clifford.at/handicraft/2014/verilatortest/test012.cc

http://svn.clifford.at/handicraft/2014/verilatortest/test012.sh

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-10T20:38:28Z

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Bad optimization, it thought this was same as (a >> (2'b11 + 2'b1)).

Fixed in git towards 3.857.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-11T21:07:37Z

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In 3.860.