Bug in evaluating (defined) expression with undef bits

[veripoolbot]

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Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 764 from https://www.veripool.org
Original Date: 2014-05-10
Original Assignee: Wilson Snyder (@wsnyder)

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This should set y=1, but verilator 6ce2a52 sets y=0 instead.

  output [3:0] y;
  localparam [3:0] p11 = 1'bx;
  assign y = ~&p11;
endmodule

Self-contained test case:

http://svn.clifford.at/handicraft/2014/verilatortest/test013.v

http://svn.clifford.at/handicraft/2014/verilatortest/test013.cc

http://svn.clifford.at/handicraft/2014/verilatortest/test013.sh

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-11T01:39:42Z

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Fixed X/Z extension under WIDTH warnings.

Pushed to git towards 3.857.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-11T21:11:16Z

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In 3.860.