Verilator internal fault related to huge shifts

[veripoolbot]

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Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 766 from https://www.veripool.org
Original Date: 2014-05-15
Original Assignee: Wilson Snyder (@wsnyder)

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Verilator d7e4bc1 fails with an internal error on the following code:

  input signed [15:0] a;
  output [15:0] y;
  assign y = (a >> 16) >>> 32'h7ffffff1;
endmodule

The error created is:

%Error: Command Failed /usr/local/bin/verilator_bin -cc -Wno-fatal -DSIMLIB_NOMEM -DSIMLIB_NOSR -DSIMLIB_NOLUT --top-module test rtl/test.v

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-16T11:11:31Z

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Fixed in git towards 3.862.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-06-11T00:57:31Z

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In 3.862.