Verilator bug in sign extending special boolean expression

[veripoolbot]

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Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 768 from https://www.veripool.org
Original Date: 2014-05-15
Original Assignee: Wilson Snyder (@wsnyder)

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This should set y=4'b1111 but Verilator d7e4bc1 sets y=4'b0001 instead.

  input signed [3:0] a;
  output [3:0] y;
  assign y = $signed(5'd1 > a-a);
endmodule

Only slight modifications in the expression make the problem disappear.

Self-contained test case:

http://svn.clifford.at/handicraft/2014/verilatortest/test015.v

http://svn.clifford.at/handicraft/2014/verilatortest/test015.cc

http://svn.clifford.at/handicraft/2014/verilatortest/test015.sh

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-16T11:11:49Z

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Fixed in git towards 3.862.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-06-11T00:57:43Z

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In 3.862.