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Another Verilator Internal Error for shift by undef value #772

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veripoolbot opened this issue May 23, 2014 · 2 comments
Closed

Another Verilator Internal Error for shift by undef value #772

veripoolbot opened this issue May 23, 2014 · 2 comments
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area: wrong runtime result resolution: fixed

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@veripoolbot veripoolbot commented May 23, 2014

Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 772 from https://www.veripool.org
Original Date: 2014-05-23
Original Assignee: Wilson Snyder (@wsnyder)

Verilator 06744b6 creates the following error:

  input [3:0] a;
  output [3:0] y;
  assign y = a << 1 <<< 0/0;
endmodule
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@veripoolbot veripoolbot commented May 24, 2014

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-24T12:01:24Z

Fixed in git towards 3.861.

Note the result in verilator may not be 'x as it isn't four-state.
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@veripoolbot veripoolbot commented Jun 11, 2014

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-06-11T00:57:53Z

In 3.862.
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