Another Verilotor bug with large shifts

[veripoolbot]

---

Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 774 from https://www.veripool.org
Original Date: 2014-05-24
Original Assignee: Wilson Snyder (@wsnyder)

---

For a=5, b=35 this should return y=0, but Verilator f705f9b returns y=8 instead:

 module issue_051(a, b, y);
   input [3:0] a;
   input [5:0] b;
   output [3:0] y;
   assign y = 64'd0 | (a << b);
 endmodule

Self-contained test case:

http://svn.clifford.at/handicraft/2014/verilatortest/test018.v

http://svn.clifford.at/handicraft/2014/verilatortest/test018.cc

http://svn.clifford.at/handicraft/2014/verilatortest/test018.sh

[veripoolbot]

---

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-06-10T23:14:04Z

---

Another massively over-shifting corner case.

Fixed in git towards 3.861.

[veripoolbot]

---

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-06-11T00:58:08Z

---

In 3.862.