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Support for SystemVerilog coverage #784

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veripoolbot opened this issue Jun 10, 2014 · 1 comment
Open

Support for SystemVerilog coverage #784

veripoolbot opened this issue Jun 10, 2014 · 1 comment

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@veripoolbot veripoolbot commented Jun 10, 2014


Author Name: Alex Solomatnikov
Original Redmine Issue: 784 from https://www.veripool.org
Original Date: 2014-06-10


Example RTL:

     covergroup cg_forward_path_control @(posedge clk);
        rd_state:   coverpoint {rd_cnt_not_zero, rd_deq} {
           illegal_bins illegal = { 2'b01 };
        }

        f_state:    coverpoint {f_uop_v, f_issue} {
           illegal_bins illegal = { 2'b01 };
        }

        rt_state: coverpoint {rt_cnt_not_zero, rt_fsm_v, rt_to_issue_v, rt_issue} {
           wildcard illegal_bins illegal = { 4'b??01 };
        }

        ry_state:  coverpoint {ry_cnt_not_zero, ry_to_issue_v, ry_issue} {
           wildcard illegal_bins illegal = { 3'b?01 };
        }

        state_cross: cross rd_state, f_state, rt_state, ry_state {
           wildcard illegal_bins ill1 = (binsof(rd_state) intersect { 2'b1? })   && ( (binsof(f_state)  intersect { 2'b?1 })   ||
                                                                                      (binsof(rt_state) intersect { 4'b???1 }) ||
                                                                                      (binsof(ry_state) intersect { 3'b??1 }) );
           wildcard illegal_bins ill2 = (binsof(f_state)  intersect { 2'b?1 })   && ( (binsof(rt_state) intersect { 4'b???1 }) ||
                                                                                      (binsof(ry_state) intersect { 3'b??1 }) );
           wildcard illegal_bins ill3 = (binsof(rt_state) intersect { 4'b???1 }) &&   (binsof(ry_state) intersect { 3'b??1 });
        }

        b2d_control: coverpoint {b2d_needed_pulse, b2d_v, b2d_v_d1, b2d_v_wait, b2d_out_en} {
           wildcard illegal_bins ill1 = { 7'b???11?? };
           wildcard illegal_bins ill2 = { 7'b?????01 };
        }
        option.per_instance = 1;
     endgroup // cg_forward_path_control

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@veripoolbot veripoolbot commented Jun 10, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-06-10T02:00:23Z


This be great to have a patch for, as I don't think there is anyone working on this.

BTW another related project I would like to see is moving the SystemPerl coverage scripts into the verilator kit itself.

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