Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

bug with bit-swap inside a large signal (more than 64 bits) #800

Closed
veripoolbot opened this issue Jul 3, 2014 · 3 comments
Closed

bug with bit-swap inside a large signal (more than 64 bits) #800

veripoolbot opened this issue Jul 3, 2014 · 3 comments

Comments

@veripoolbot
Copy link
Contributor

@veripoolbot veripoolbot commented Jul 3, 2014


Author Name: Jie Xu (@jiexu)
Original Redmine Issue: 800 from https://www.veripool.org
Original Date: 2014-07-03
Original Assignee: Wilson Snyder (@wsnyder)


Verilator generates incorrect code for the following:


// ---------------------------------------------------------------------------
// combinational blocks / continuous assignament
// ---------------------------------------------------------------------------
always_comb begin: b_test
     logic [127:0] tmpp;
     logic [127:0] tmp;
     tmp  = 0;
     tmpp = 0;

     tmp[63:0]  = val;
     tmpp[63:0] = val;

     tmpp[63:0] = {tmp[0+:32], tmp[32+:32]};
     tmp[63:0]  = {tmp[0+:32], tmp[32+:32]};
end


@tmp@ and @TMPP@ will be different in the simulation.

A test case can be pulled here https://github.com/jiexu/verilator/tree/bitsSwap

@veripoolbot
Copy link
Contributor Author

@veripoolbot veripoolbot commented Jul 4, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-07-04T13:18:18Z


One of the optimization steps got confused by the same var on LHS and RHS. "-Ox" could be used to disable this and get the correct result.

Fixed in git towards 3.863.

@veripoolbot
Copy link
Contributor Author

@veripoolbot veripoolbot commented Jul 4, 2014


Original Redmine Comment
Author Name: Jie Xu (@jiexu)
Original Date: 2014-07-04T13:23:14Z


thanks.

@veripoolbot
Copy link
Contributor Author

@veripoolbot veripoolbot commented Sep 21, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-09-21T13:10:33Z


In 3.864.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Linked pull requests

Successfully merging a pull request may close this issue.

None yet
2 participants
You can’t perform that action at this time.