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bug with bit-swap inside a large signal (more than 64 bits) #800
Verilator generates incorrect code for the following:
A test case can be pulled here https://github.com/jiexu/verilator/tree/bitsSwap
Original Redmine Comment
One of the optimization steps got confused by the same var on LHS and RHS. "-Ox" could be used to disable this and get the correct result.
Fixed in git towards 3.863.